About Javelin

Javelin Design Automation is a privately-held Electronic Design Automation (EDA) company established in July 2004, based in Silicon-Valley, with R&D located in Ontario, Canada. Javelin’s mission is to deliver timely, accurate physical feasibility feedback from the earliest architecture stage for higher-quality Systems-in-Silicon. Javelin’s System Physical Prototyping™ (SPP) technology provides a first-of-its-kind specification-driven platform for timely and efficient collaboration of architectural, logic and physical design data. The platform is used by customer design teams to explore, evaluate, and optimize their ASIC and SoC designs, to hand-off feasible, high-quality designs to their choice of multiple downstream implementation flows. It helps them achieve higher chip Quality-of-Results (QoR) more quickly and efficiently, at less cost. The total available market for SPP is estimated to be $500M to 800M, and it is predicted to be one of the fastest-growing segments in the Electronic Design Automation (EDA) industry.

The Problem: Architecture and Design Decisions are made with late and limited physical feedback

To thrive in today’s diverse markets, electronics companies must deliver differentiated and increasingly complex products in ever-shortening windows, but no longer can reap large differentiation by implementing the same architecture or design in smaller silicon processes. Increasing access to quality silicon foundries, rich IP choices, and integrated implementation tool flows have leveled the playing field, forcing companies to focus on differentiating at the architecture-level to deliver the right mix of end-product features, performance, and cost within tight market windows.


According to analyst research, only 20% of designs succeed in meeting the desired design objective, while 30% are seriously compromised, and 50% or more of all designs never see production. These statistics reflect the current reality that many chip designs and blocks that appear sound from an architectural and logical perspective are physically inferior or even infeasible. However those very same designs routinely enter companies’ design implementation flows. Many of these problems are not detected early enough using traditional tools and so are not flagged until late in the design process. At this late stage, the flawed designs must be sent back for re-design, causing long, serial iterations that add weeks or months to the design schedule. These designs frequently result in lower product performance, higher costs, and loss of key product features. Resulting product compromises and time-to-market delays significantly reduce selling price, margins and marketshare.