Javelin System Physical Prototyping technology enables companies’ design teams to focus their efforts on maximizing differentiation of their products from the very start. Unlike other solutions, Javelin works with partial design data, and can be easily operated easily by architecture and logic design teams early in the design phase, minimizing issues that would become costly if addressed further downstream and late in the flow. Leveraging all that is collectively known of the design early on, Javelin provides designers with fast, timely and quality feedback for physical feasibility as they explore multiple possible architectures and design structures. Armed with these insights and understanding, designers can make better design decisions and tradeoffs to deliver higher-quality QOR Chips, in shorter time, and at lower chip and project cost. Javelin is already in production use today by select Customer Partners, who have taped-out quality Chips in multiple processes ranging from 0.13um down to 65nm.

RTL Coding and RTL Architecture: Major timing and congestion problems are fixed in RTL code 
Improvement: 20-40%

RTL Synthesis: Proper synthesis approach and physical synthesis 
Improvement: 10-20%

Gate Placement and Logic Optimization: Cannot resolve major routing or congestion problems 
Improvement: 10% typical

Gate-level Optimization: Low-level optimization techniques 
Improvement: 5% typical