TruePro is tailored for physically-aware chip architects, RTL designers, timing leads, and chip integrators to validate that the chip-plans and blocks are physically close-able.  This is accomplished by enabling progressive prototyping of the chip-plan and/or blocks-in-chip context as block netlists become available.  TruePro’s state-of-the-art, fully multithreaded and multicore Organic Placement and Virtual Route engines provide fast QoR feedback on congestion and timing of these early netlists. This concurrent, hierarchical chip-planning with block-prototyping-in-chip context methodology is called “Progressive Prototyping”. This enables design teams to quickly predict, detect, analyze and fix identified issues in the chip plan well before final netlists are available.

Features Include:

• All TruePlan features
• Timing , Congestion and Power driven legalized cell placement
• Build it timing engine with detailed cross probing to layout view
• Congestion analysis
• Clock tree visualization
• Timing optimization
• Exports formats including (Verilog, LEF/DEF, SPEF, PDEF, .lib and sdc)