Most troubling Chip Planning-Prototyping issue? (choose one)
- Number of Voters
- 9
- First Vote
- Sunday, 01 June 2008 23:49
- Last Vote
- Monday, 09 February 2009 11:35
Most troubling Chip Planning-Prototyping issue? (choose one)
| Hits | Percent | Graph |
|---|---|---|
| Starting Too Late | ||
| 2 | 22.2% | |
| Incomplete Data | ||
| 2 | 22.2% | |
| Macro Placement | ||
| 2 | 22.2% | |
| RTL Partitioning | ||
| 1 | 11.1% | |
| Congestion | ||
| 1 | 11.1% | |
| Multi-Voltage Domains | ||
| 1 | 11.1% | |
| Power Planning | ||
| 0 | 0% | |
| SDC Quality | ||
| 0 | 0% | |
| Timing Convergence | ||
| 0 | 0% | |
| Pin Assignment | ||
| 0 | 0% | |
| Bus Planning | ||
| 0 | 0% | |
| Package Selection | ||
| 0 | 0% | |